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commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 1 may 2004 IDTCV123 commercial temperature range programmable flexpc? clock for p4 processor xtal osc amp sm bus controller control logic cpu clk output buffers stop logic x1 x2 sdata sclk v tt_pwrgd #/pd fsa.b.c i ref cpu[1:0] ref[0:1] cpu_itp/src6 pll1 ssc n programmable itp_en src clk output buffer stop logic 48mhz/96mhz output buffer i ref src[6:0] 48mhz dot96 pll2 ssc n programmable pll3 pci[5:0], pcif[2:0] sata_src the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-6538/4 features: ? one high precision pll for cpu, with ssc and n program- mable ? one high precision pll for src/pci/sata, ssc and n pro- grammable ? one high precision pll for 96mhz/48mhz ? band-gap circuit for differential outputs ? supports spread spectrum modulation, down spread 0.5% ? supports smbus block read/write, index read/write ? selectable output strength for ref ? allows for cpu frequency to change to a higher frequency for maximum system computing power ? available in ssop package functional block diagram description: IDTCV123 is a 56 pin clock device. the cpu output buffer is designed to support up to 400mhz processor. this chip has three plls inside for cpu/ src/pci, sata, and 48mhz/dot96 io clocks. one dedicated pll for serial ata clock provides high accuracy frequency. this device also implements band-gap referenced i ref to reduce the impact of v dd variation on differential outputs, which can provide more robust system performance. static pll frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. each cpu/src/pci, sata clock has its own spread spectrum selection, which allows for isolated changes instead of affecting other clock groups. outputs: ? 2*0.7v current ?mode differential cpu clk pair ? 8*0.7v current ?mode differential src clk pair, one dedicated for sata ? one cpu_itp/src selectable clk pair ? 8*pci, 3 free running, 33.3mhz ? 1*96mhz, 1*48mhz ? 2*ref key specification: ? cpu/src clk cycle to cycle jitter < 85ps ? sata clk cycle to cycle jitter < 85ps ? pci clk cycle to cycle jitter < 250ps ? static pll frequency divide error < 114 ppm ? static pll frequency divide error for 48mhz < 5 ppm
commercial temperature range 2 IDTCV123 programmable flexpc? clock for p4 processor pin configuration symbol description min max unit v dda 3.3v core supply voltage 4.6 v v ddin 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ssop top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ref0/fsc gnd_ref x1 x2 v dd _ref sdat scl cpu0 cpu0# v dd _cpu cpu1 cpu1# cpu_itp#/src6# v dd _src src5 src5# gnd_src src4# src3 src3# v dd _src 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pci0 pci1 pci3 pci4 pci5 gnd_pci v tt _p wrgd# / pd v dd 48 usb48/fsb gnd 48 dot96 dot96# src1 src1# v dd _src src2 src2# sata_src sata_src# src4 gnd_pci v dd _pci pci2 v dd _pci *test_sel/pcif0 itp_en/pcif1 src0 src0# gnd_src cpu_itp/src6 ref1/fsa gnd_cpu iref gnd_a v dd _a frequency selection table fsc, b, a cpu mode, mhz src4 src[3:1], src[7:5] pci usb dot96 ref 101 100 100 100 33.3 48 96 14.318 001 133 100 100 33.3 48 96 14.318 011 166 100 100 33.3 48 96 14.318 010 200 100 100 33.3 48 96 14.318 000 266 100 100 33.3 48 96 14.318 100 333 100 100 33.3 48 96 14.318 110 400 100 100 33.3 48 96 14.318 111 reserve 100 100 33.3 48 96 14.318 itp_en pin 38 pin 39 1 cpuc2_itp cput_itp 0 srcc6 srct6 test clarification table hw sw test_sel/ test select pciclk_f0 bit b6b6 output comments 0 0 normal normal operation 1 x hi-z power-up with test_sel =1 to enter test mode. cycle power with test_sel = 0 to disable test mode 0 1 hi-z if test_sel hw pin is 0 during power-up, test mode can be invoked through b6b6. cycle power with test_sel = 0 to disable test mode. * = internal pull down
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 3 pin description pin number name type description 1 pci0 out pci clock 2 pci1 out pci clock 3v dd _pci pwr 3.3v 4v ss _pci gnd gnd 5 pci2 out pci clock 6 pci3 out pci clock 7 pci4 out pci clock 8 pci5 out pci clock 9v ss _pci gnd gnd 10 v dd _pci pwr 3.3v 11 test_sel/pcif0 i/o test select (sampled at v tt _p wrgd # assertion), see test_sel table. pci clock afterward, free running. 12 itp_en/pcif1 out pin38, 39, cpu_itp/src6 select (sampled on v tt _p wrgd # assertion), high = cpu_2pci clock. pci clock afterward, running. 13 v dd 48 pwr 3.3v 14 usb48 /fs_b i/o 48mhz clock/ fs_b input 15 v ss 48 gnd gnd 16 dot96t out 96mhz 0.7v current mode differential clock output 17 dot96c out 96mhz 0.7v current mode differential clock output 18 v tt _p wrgd #/pd i/o 3.3v lvttl input is a level-sensitive strobe used to latch the fs_a, fs_b, fs_c, test_sel and itp_en inputs, v tt _p wrgd # is low assertion/ after v tt _p wrgd # assertion, becomes a real-time input for asserting power down (active high). 19 srct0 out differential serial reference clock 20 srcc0 out differential serial reference clock 21 srct1 out differential serial reference clock 22 srcc1 out differential serial reference clock 23 v dd _src pwr 3.3v 24 v ss _src gnd gnd 25 srct2 out differential serial reference clock 26 srcc2 out differential serial reference clock 27 srct_sata out sata clock 28 srcc_sata out sata clock 29 v dd _src pwr 3.3v 30 srcc3 out differential serial reference clock 31 srct3 out differential serial reference clock 32 srcc4 out differential serial reference clock 33 srct4 out differential serial reference clock 34 v ss _src gnd gnd 35 srcc5 out differential serial reference clock 36 srct5 out differential serial reference clock 37 v dd _src pwr 3.3v 38 cpuc2_itp/ srcc6 out selectable cpu or src differential clock output. itp_en=0 @ v tt _p wrgd # assertion = srcc6. 39 cput2_itp/ srct6 out selectable cpu or src differential clock output. itp_en=0 @ v tt _p wrgd # assertion = srct6. 40 v dd _a pwr 3.3v 41 v ss _a gnd gnd 42 iref out reference current for differential output buffer
commercial temperature range 4 IDTCV123 programmable flexpc? clock for p4 processor pin description (cont.) pin number name type description 43 cpuc1 out host 0.7v current mode differential clock output 44 cput1 out host 0.7v current mode differential clock output 45 v dd _cpu pwr 3.3v 46 cpuc0 out host 0.7v current mode differential clock output 47 cput0 out host 0.7v current mode differential clock output 48 v ss _cpu gnd gnd 49 scl in sm bus clock 50 sda i/o sm bus data 51 xtal_out out xtal output 52 xtal_in in xtal input 53 v ss _ref gnd gnd 54 ref1/ fsa i/o 14.318 mhz reference clock output. cpu frequency selection at v tt _p wrgd # assertion. 55 ref0/ fsc i/o 14.318 mhz reference clock output. cpu frequency selection at v tt _p wrgd # assertion. 56 v dd _ref pwr 3.3v index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n, (0 is not valid 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit30-37). bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master d3h 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes), power on is 8 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop index byte write setting bit[11:18] = starting address, bit[20:27] = 01h. index byte read setting bit[11:18] = starting address. after reading back the first data byte, master issues stop bit.
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 5 control registers n programming procedure ? use index byte write. for n programming, the user only needs to access byte17, byte 25, and byte8. 1. write byte17 for cpu pll n, cpu f = n* resolution, see resolution table below byte17. 2. write byte25 for src pll n, src f = n*0.666667, pci = src f /3, sata f = src f. 3. enable n programming bit, byte8 bit1. once this bit is enabled, any n value will be changed on the fly. center spread only works when the n programming bit is enabled. down spread is ok even n programming bit is disabled it is ok to change n value to any value on the bench test board. in the system, idt recommends the stepping change. it is unkn own how much the system can sustain for each stepping change; the estimate is about 5. if the n changes too much in one step, the system wil l likely hang. note that sata is with src pll. this sata hard drive might not operate during src n programming. most of the bytes, from byte8-byte31, are used to adjust output waveforms and ssc modulation profiles. the power on setting wil l be changed according to each power on frequency selection. to avoid mistakes, don?t write on those byte (be careful about block write). it is sugge sted to use the index byte write to access bytes. ssc magnitude control, smc smc[2:0] 000 -0.25 001 -0.5 010 -0.75 011 -1 100 0.125 101 0.25 110 0.375 111 0.5 fs_c, b, a cpu 101 100 001 133 011 166 010 200 000 266 100 333 110 400 111 reserve frequency selection table resolution cpu (mhz) resolution n = 100 0.666667 150 133 0.666667 200 166 1.333333 125 200 1.333333 150 266 1.333333 200 333 2.666667 125 400 2.666667 150
commercial temperature range 6 IDTCV123 programmable flexpc? clock for p4 processor byte 0 bit output(s) affected description/function 0 1 type power on 7 cput2, cpuc2/ output enable tristate enable rw 1 srct6, srcc6 6 srct5, srcc5 output enable tristate enable rw 1 5 srct4, srcc4 output enable tristate enable rw 1 4 srct3, srcc3 output enable tristate enable rw 1 3 satat, satac output enable tristate enable rw 1 2 srct2, srcc2 output enable tristate enable rw 1 1 srct1, srcc1 output enable tristate enable rw 1 0 srct0, srcc0 output enable tristate enable rw 1 byte 2 bit output(s) affected description/function 0 1 type power on 7 pci5 output enable tristate enable rw 1 6 pci4 output enable tristate enable rw 1 5 pci3 output enable tristate enable rw 1 4 pci2 output enable tristate enable rw 1 3 pci1 output enable tristate enable rw 1 2 pci0 output enable tristate enable rw 1 1 pcif1 output enable tristate enable rw 1 0 pcif0 output enable tristate enable rw 1 byte 1 bit output(s) affected description/function 0 1 type power on 7 reserved rw 1 6 dot96t, dot96c output enable tristate enable rw 1 5 usb48 output enable tristate enable rw 1 4 ref0 output enable tristate enable rw 1 3 ref1 output enable tristate enable rw 1 2 cput1, cpuc1 output enable tristate enable rw 1 1 cput0, cpuc0 output enable tristate enable rw 1 0 spread spectrum spread spectrum enable off on rw 0 byte 3 bit output(s) affected description / function 0 1 type power on 7 cput2, cpuc2/ free-running stoppable rw 0 srct6, srcc6 6 srct5, srcc5 free-running stoppable rw 0 5 srct4, srcc4 free-running stoppable rw 0 4 srct3, srcc3 free running, not affected by free-running stoppable rw 0 3 satat, satac pci/src_stop bit (byte6, bit3) free-running stoppable rw 0 2 srct2, srcc2 free-running stoppable rw 0 1 srct1, srcc1 free-running stoppable rw 0 0 srct0, srcc0 free-running stoppable rw 0
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 7 byte 4 bit output(s) affected description / function 0 1 type power on 7 reserved 1 6 dot96 dot96 power down drive mode driven in power down tristate rw 0 5 pcif1 free running, not affected by free-running stoppable rw 0 4 pcif0 pci/src_stop bit (byte6, bit3) free-running stoppable rw 0 3 reserved 1 2 reserved 1 1 reserved 1 0 reserved 1 byte 5 bit output(s) affected description / function 0 1 type power on 7 stopped src drive mode in pci_stop driven tristate rw 0 6 reserved 0 5 reserved 0 4 reserved 0 3 src src p wrdwn drive mode driven in power down tristate in power down rw 0 2 cpu_itp cput2 p wrdwn drive mode driven in power down tristate in power down rw 0 1 cpu1 cput1 p wrdwn drive mode driven in power down tristate in power down rw 0 0 cpu0 cput0 p wrdwn drive mode driven in power down tristate in power down rw 0 byte 7 bit output(s) affected description / function 0 1 type power on 7 revision id 0 6 revision id 0 5 revision id 0 4 revision id 0 3 vendor id 0 2 vendor id 1 1 vendor id 0 0 vendor id 1 byte 6 bit output(s) affected description / function 0 1 type power on 7 reserved 0 6 test select test select normal all clk outputs hi-z 0 5 ref1 strength select 1x 2x 1 4 ref0 strength select 1x 2x 1 3 pci/src_stop stop all stoppable pci/srct clocks stop running 1 2 fs_c latch read back r 1 fs_b latch read back r 0 fs_a latch read back r
commercial temperature range 8 IDTCV123 programmable flexpc? clock for p4 processor byte 17 bit output(s) affected description / function 0 1 type power on 7 cpu_n7, msb rw 6 cpu_n6 rw 5 cpu_n5 rw 4 cpu_n4 rw 3 cpu_n3 rw 2 cpu_n2 rw 1 cpu_n1 see resolution table rw 0 cpu_n0, lsb cpu clk = n* resolution rw bytes 10-16: output waveform adjustment. don't write over. bytes 18-24: output waveform adjustment. don't write over. byte 8 bit output(s) affected description / function 0 1 type power on 7 src ssc enable only valid when byte1 bit0 is 1 disable enable rw 1 6 cpu pll power down normal power down rw 0 5 src pll power down normal power down rw 0 4 usb pll power down normal power down rw 0 3 usb48 usb 48 strength control 1x 2x rw 0 2 reserve rw 0 1 n programming enable disable enable rw 0 0 one cycle read disable enable rw 0 byte 9 bit output(s) affected description / function 0 1 type power on 7 must be 0 must be 0 rw 0 (must be 0) 6 cpu smc2 rw 0 5 cpu smc1 see smc table rw 0 4 cpu smc0 cpu pll ssc control rw 1 3 reserve rw 0 2 src smc2 rw 0 1 src smc1 see smc table rw 0 0 src smc0 src/pci ssc control rw 1
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 9 byte 25 bit output(s) affected description / function 0 1 type power on 7 src_n7, msb rw 6 src_n6 rw 5 src_n5 rw 4 src_n4 rw 3 src_n3 rw 2 src_n2 100mhz n= 150 rw 1 src_n1 resolution = 0.666667 rw 0 src_n0, lsb src f = n*src resolution rw bytes 26-31: output waveform adjustment. don't write over.
commercial temperature range 10 IDTCV123 programmable flexpc? clock for p4 processor symbol parameter test conditions min. typ. max. unit v ih input high voltage 3.3v 5% 2 ? v dd + 0.3 v v il input low voltage 3.3v 5% v ss - 0.3 ? 0.8 v v ih _fs low voltage, high threshold for fsa.b.c test_mode 0.7 ? v dd + 0.3 v v il _fs low voltage, low threshold for fsa.b.c test_mode v ss - 0.3 ? 0.35 v i il input leakagecurrent 0< v in < v dd , no internal pull-up or pull-down ?5 ? +5 ma i dd3.3op operating supply current full active, c l = full load ? ? 400 ma i dd3.3pd powerdown current all differential pairs driven ? ? 70 ma all differential pairs tri-stated ? ? 12 f i input frequency (1) v dd = 3.3v ? 14.31818 ? mhz l pin pin inductance (2) ?? 7 nh c in logic inputs ? ? 5 c out input capacitance (2) output pin capacitance ? ? 6 pf c inx x1 and x2 pins ? ? 5 t stab clock stabilization (2,3) from v dd power-up or de-assertion of pd# to first clock ? ? 1.8 ms modulation frequency (2) triangular modulation 30 ? 33 khz t drive _src (2) src output enable after pci_stop# de-assertion ? ? 15 ns t drive _pd# (2) cpu output enable after pd# de-assertion ? ? 300 us t fall _pd# (2) fall time of pd# ? ? 5 ns t rise _pd# (3) rise time of pd# ? ? 5 ns t drive _cpu_stop# (2) cpu output enable after cpu_stop# de-assertion ? ? 10 us t fall _cpu_stop# (2) fall time of pd# ? ? 5 ns t rise _cpu_stop# (3) rise time of pd# ? ? 5 ns electrical characteristics - input / supply / common output parameters following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5% notes: 1. input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. 2. this parameter is guaranteed by design, but not 100% production tested. 3. see timing diagrams for timing requirements.
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 11 symbol parameter test conditions min. typ. max. unit z o current source output impedance (2) v o = v x 3000 ? ? ? v oh3 output high voltage i oh = -1ma 2.4 ? ? v v ol3 output low voltage i ol = 1ma ? ? 0.4 v v high voltage high (2) statistical measurement on single-ended signal using 660 ? 850 mv v low voltage low (2) oscilloscope math function ?150 ? 150 v ovs max voltage (2) measurement on single-ended signal using absolute value ? ? 1150 mv v uds min voltage (2) ?300 ? ? v cross(abs) crossing voltage (abs) (2) 250 ? 550 mv d - v cross crossing voltage (var) (2) variation of crossing over all edges ? ? 140 mv ppm long accuracy (2,3) see t period min. - max. values ?300 ? 300 ppm 400mhz nominal/spread 2.4993 ? 2.5008 333.33mhz nominal/spread 2.9991 ? 3.0009 266.66mhz nominal/spread 3.7489 ? 3.7511 t period average period (3) 200mhz nominal/spread 4.9985 ? 5.0015 ns 166.66mhz nominal/spread 5.9982 ? 6.0018 133.33mhz nominal/spread 7.4978 ? 7.5023 100mhz nominal/spread 9.997 ? 10.003 96mhz nominal 10.4135 ? 10.4198 400mhz nominal/spread 2.4143 ? ? 333.33mhz nominal/spread 2.9141 ? ? 266.66mhz nominal/spread 3.6639 ? ? 200mhz nominal/spread 4.9135 ? ? t absmin absolute min period (2,3) 166.66mhz nominal/spread 5.9132 ? ? ns 133.33mhz nominal/spread 7.4128 ? ? 100mhz nominal/spread 9.912 ? ? 96mhz nominal 10.1635 ? ? t r rise time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation (2) ? ? 125 ps d-t f fall time variation (2) ? ? 125 ps d t3 duty cycle (2) measurement from differential waveform 45 ? 55 % t sk 3 skew (2) v t = 50% ? ? 100 ps t jcyc - cyc jitter, cycle to cycle (2) measurement from differential waveform ? ? 85 ps electrical characteristics - cpu, src, and dot96 0.7 current mode differential pair (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf notes: 1. src clock outputs run only at 100mhz or 200mhz. specs for 133.33 and 166.66 do not apply to src clock pair. 2. this parameter is guaranteed by design, but not 100% production tested. 3. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range 12 IDTCV123 programmable flexpc? clock for p4 processor symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 33.33mhz output nominal 29.991 ? 30.009 ns 33.33mhz output spread 29.991 ? 30.1598 v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t sk1 skew (1) v t = 1.5v ? ? 500 ps t jcyc - cyc jitter (1) v t = 1.5v ? ? 250 ps electrical characteristics - pciclk / pciclk_f following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 48mhz output nominal 20.8257 ? 20.834 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -29 ? ? ma v oh at max. = 3.135v ? ? -23 i ol output low current v ol at min. = 1.95v 29 ? ? ma v ol at max. = 0.4v ? ? 27 edge rate (1) rising edge rate 1 ? 2 v/ns edge rate (1) falling edge rate 1 ? 2 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % electrical characteristics, 48mhz, usb following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 13 symbol parameter test conditions min. typ. max. unit ppm long accuracy (1) see tperiod min. - max. values ? ? 300 ppm t period clock period 14.318mhz output nominal 69.827 ? 69.855 ns v oh output high voltage (1) i oh = -1ma 2.4 ? ? v v ol output low voltage (1) i ol = 1ma ? ? 0.4 v i oh output high current (1) v oh at min. = 1v, v oh at max. = 3.135v -33 ? -33 ma i ol output low current (1) v ol at min. = 1.95v, v ol at max. = 0.4v 30 ? 38 ma t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t sk1 skew (1) v t = 1.5v ? ? 500 ps d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter (1) v t = 1.5v ? ? 1000 ps electrical characteristics - ref-14.318mhz following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf note: 1. this parameter is guaranteed by design, but not 100% production tested. pci stop functionality if pcif (2:0) and src clocks are set to be free-running through smbus programming, they will ignore the pci_stop register bit. pci_stop cpu cpu# src src# pcif/pci usb dot96 dot96# ref (byte 6 bit 3) 1 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 0 normal normal i ref * 6 or float low low 48mhz normal normal 14.318mhz
commercial temperature range 14 IDTCV123 programmable flexpc? clock for p4 processor pd, power down pd is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. when pd is asserted high all clocks will be driven low before turning off the vco. in pd de-assertion all clocks will start without glitches. pd assertion p wrdwn cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 p wrdwn cpu cpu# src src# pcif/pci usb dot96 dot96# ref 0 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 1i ref * 2 or float float i ref * 2 or float float low low i ref * 2 or float float low
commercial temperature range IDTCV123 programmable flexpc? clock for p4 processor 15 pd de-assertion the time from the de-assertion of pd or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mod e control bit for pd tristate is programmed to ?1? the stopped differential pair must first be driven high to a minimum of 200mv in less than 300s of pd deasse rtion. p wrdwn cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms t drive_pwrdwn <300 s, <200mv
commercial temperature range 16 IDTCV123 programmable flexpc? clock for p4 processor ordering information xxx xx package pv small shrink outline package programmable flexpc? clock for p4 processor 123 device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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